1. Field
This disclosure relates generally to integrated circuits, and more specifically, to integrated circuits in which speedpath operations are critical.
2. Related Art
In many integrated circuits, certain operations must occur within a certain time. Setup and hold times are examples. Another typical one is the speed of performing a read in a memory. But there additionally many operations that need to occur by a certain time or within a certain time window in order to achieve an overall speed requirement. In these cases, there is often one signal path that is most critical in achieving the needed timing. This is often called the critical speedpath. The critical speedpath is the one that will generally receive the most attention in a design. Of course design mistakes can occur so that either the speedpath is not optimized or is not fully understood. With or without a mistake though, one of the critical speedpaths (an integrated circuit is likely to have more than one) will likely be the cause of the integrated circuit to not meet its specification and be considered a failed device. This will often occur due to process variations that result in the timing through the critical speedpath being too slow. In some designs, a failure may result from the timing actually being too fast. Whether the timing is too fast or too slow for the design, the result is costly.
Accordingly there is a need for providing a technique for reducing the occurrences of not achieving the desired timing in a critical speedpath.